`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/11/05 18:14:48
// Design Name: 
// Module Name: thirtytwo_bit_lookforward_fulladd
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module thirtytwo_bit_lookforward_fulladd(A,B,CI,S,CO);
  input [31:0] A,B;
  output [31:0] S;
  input CI;
  output CO;
  wire c_tem;
 //reg [31:0] S;
  //reg CO;
 
  sixteen_bit_fulladd
   S1(A[15:0],B[15:0],CI,S[15:0],c_tem);
  sixteen_bit_fulladd
   S2(A[31:16],B[31:16],c_tem,S[31:16],CO);
endmodule
